1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
To control electric field concentration at the device end (chip end), in one known high voltage structure, a field limiting ring (FLR) that is a floating (floating electric potential) p-type region is disposed in plural in an edge termination region that surrounds the periphery of an active region. In another known high voltage structure, a field plate (FP), which is a metal electrode or a polysilicon (poly-Si) electrode connected to an FLR, is disposed. The FP controls that way that the depletion layer spreads, prevents degradation of the breakdown voltage, and has a function of controlling the surface charge distribution and property changes consequent to the surface charge.
A structure of the edge termination region of a semiconductor device will be described. FIG. 35 is a cross sectional view of a structure of an edge termination region of a conventional semiconductor device. The conventional semiconductor device depicted in FIG. 35 includes a high voltage structure formed by FLRs 103 and FPs 106, in an edge termination region 112 surrounding a periphery of an active region 111. The active region 111 is a region in which current flows during the ON state. The edge termination region 112 is a region that relaxes the electric field of a substrate front-surface side of an n−-type drift region 101 and maintains the breakdown voltage. The FLR 103 is disposed in plural, concentrically surrounding the periphery of the active region 111, in a surface layer of a front surface of an n−-type semiconductor substrate (semiconductor chip) 110 that becomes the n−-type drift region 101.
In the edge termination region 112, the front surface of the n−-type semiconductor substrate 110 is covered by an interlayer insulating film 107. The FP 106 contacts the FLR 103 via a contact hole that penetrates the interlayer insulating film 107 in a direction of depth. The FP 106 is disposed for each the FLRs 103. Further, the FP 106 extends inwardly (the active region 111 side) or outwardly (the chip end side), or both, on the interlayer insulating film 107. Reference numeral 102 represents a p-type region configuring a pn junction (main junction) with the n−-type drift region 101, in the active region 111. Reference numerals 104, 105, and 108 represent a p-type channel stop region, a local oxidation of silicon (LOCOS), and a passivation film, respectively.
A principle of operation at the edge termination region 112 where the FLRs 103 are disposed will be described. FIG. 36 is a diagram depicting the principle of operation at the edge termination region of a conventional semiconductor device. In FIG. 36, (a) and (b) respectively depict temporally from the left, transition of electric field distribution and charge distribution corresponding to (c). In FIG. 36, (c) depicts temporally by broken lines 121a and 121b, end positions of a depletion layer 121 extending outwardly when the semiconductor device is OFF. The horizontal axes in FIG. 36 represent a distance r expressing positional relations of parts, in a direction from an inner side toward an outer side. At (a), the vertical axis represents electric field strength E. At (b), the vertical axis represents charge q and an upper quadrant above the horizontal axis represents negative charge ND while a lower quadrant below the horizontal axis represents positive charge NA. Further, at (c), the vertical axis represents a depth d of the front surface of the n−-type semiconductor substrate 110.
When the semiconductor device is OFF and a pn junction (hereinafter, main junction) 120 between the p-type region 102 and the n−-type drift region 101 in the active region 111 is reverse biased, the depletion layer 121 is formed along the main junction 120, and extends outwardly accompanying an increase in the reverse biasing. Furthermore, although the electric field strength near an end of the active region 111 (near an end 102a of the p-type region 102) increases ((a) of FIG. 36) accompanying the reverse biasing, near an end of the active region 111, before avalanche breakdown occurs, the depletion layer 121 reaches the innermost FLR 103 (broken line 121a in (c) of FIG. 36). As a result, the p-type region 102 and the innermost FLR 103 punchthrough, suppressing the peak electric field at the end 102a of the p-type region 102.
When the depletion layer 121 reaches the innermost FLR 103, holes (positive holes) in the innermost FLR 103 flow to the active region 111 and positive charge NA is lost (portion indicated by reference numeral 131 in (b) of FIG. 36). To compensate for the lost positive charge NA of the innermost FLR 103, the depletion layer 121 further extends outwardly (broken line 121b in (c) of FIG. 36). When the reverse biasing is further increased, although the electric field strength increases near an outer end 103a of the inner most FLR 103, before avalanche breakdown occurs at the outer end 103a of the FLR 103, the depletion layer 121 further reaches an outward FLR 103 (not depicted in (c) of FIG. 36). As a result, the FLRs 103 punchthrough, suppressing the peak electric field at the outer end 103a of the innermost FLR 103.
Thus, portions contributing to the critical electric field strength are sequentially moved outward to the outer ends 103a of the FLRs 103 such that avalanche breakdown occurs at the outermost FLR 103, whereby the electric field near the end of the active region 111 relaxes, realizing high breakdown voltage. The breakdown voltage of the semiconductor device is determined by the applied voltage that causes avalanche breakdown at the outermost FLR 103. Further, as described above, since the way the depletion layer 121 extends consequent to the balance of the charge q of the FLRs 103 is determined, the adverse effects of the charge (hereinafter, surface charge) at the surface of the interlayer insulating film 107, the interface of the interlayer insulating film 107 and the n−-type semiconductor substrate 110, etc. is remarkable. Therefore, the FPs 106 and the FLRs 103 are connected respectively to reduce the adverse effects of the surface charge.
In a device proposed (for example, refer to Japanese Patent No. 5135663) as another semiconductor device equipped with FPs, a trench disposed in the edge termination region is filled with an insulating film and a FP is embedded in a recess disposed in the insulating film. In Japanese Patent No. 5135663, the depth of the FP in the insulating film is suitably adjusted, whereby a range of the quantity of surface charge allowed under the environment at the time of actual use is set and breakdown voltage that is nearly an ideal breakdown voltage (voltage causing avalanche breakdown in an ideal state when no surface charge is present) is set.